[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY FullAdder1 is port(In1, In2: in std_logic_vector(31 downto 0):=(others=>'0');
                          CarryIn: in std_logic_vector(0 downto 0):=(others=>'0');
                          Sum: out std_logic_vector(31 downto 0):=(others=>'0');
                          CarryOut: out std_logic:='0');
 end FullAdder1;

ARCHITECTURE FullAdder_1 of FullAdder1 is
    signal tmp: std_logic_vector(32 downto 0);

    BEGIN
       tmp <= std_logic_vector(to_signed(to_integer(signed(In1)) 
                             + to_integer(signed(In2)) 
                             + to_integer(signed(CarryIn)), 33));
       CarryOut <= tmp(32);
       Sum <= tmp(31 downto 0);
END FullAdder_1;
[/code]
[code]
library ieee;
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;

entity pc is port (inPC: in std_logic_vector(31 downto 0);
                   outPC: out std_logic_vector(31 downto 0);
                   clk: in std_logic:='0';
                   reset: in std_logic:='0');
end pc;

architecture pc_1 of pc is
begin
   reg:process(clk, reset)
   begin
     if (reset = '1') then       
       outPC <= std_logic_vector(to_signed(-4,32)); 
     elsif (clk'event and clk='1') then
        outPC <= inPC;
     end if;  
end process;
end pc_1;
[/code]
[code]
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity instrMemory is
  port (
        Addr : in std_logic_vector(31 downto 0);
        C : out std_logic_vector(31 downto 0));
end instrMemory; 
architecture arch1 of instrMemory is
  type instr_array is array (0 to 15) of std_logic_vector (31 downto 0);
  constant instrmem: instr_array := (
  "00000000010001100010000000100000", -- value of 00000000010001100010000000100000 (0x00462020)(add $4,$2,$6)
  "00000000010001100010100000100010", -- value of 00000000010001100010100000100010 (0x00462822)(sub $5,$2,$6)
  "11111111111111111111111111111111",
  "00000000000000000000000000000000",
  "11111111111111111111111111111111",
  "00000000101001100010000000100000", -- value of 00000000101001100010000000100000 (0x00A62020)(add $4,$5,$6)
  "11111111111111111111111111111111",
  "10101100111001100000000000000100", -- value of 1010110011100110000000000000100 (0xACE60004)(sw $6,4(&7))
  "11111111111111111111111111111111",
  "10001100101001001111111111111100", -- value of 10001100101001001111111111111100 (0x8CA4FFFC)(lw $4,-4($5))
  "11111111111111111111111111111111",
  "11111111111111111111111111111111",
  "11111111111111111111111111111111",
  "11111111111111111111111111111111",
  "11111111111111111111111111111111",
  "11111111111111111111111111111111");
begin
  C <= instrmem(to_integer(unsigned(Addr))) when to_integer(unsigned(Addr)) >= 0 else x"00000000";
end arch1; 
[/code]
[code]
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

entity regfile1 is
generic (dw : natural := 4; 
         size : natural := 4;
         adrw : natural := 2);

port (Datain : in std_logic_vector(dw-1 downto 0):=(others=>'0');
      rAddr1 : in std_logic_vector(adrw-1 downto 0):=(others=>'0');
      rAddr2 : in std_logic_vector(adrw-1 downto 0):=(others=>'0');
      wAddr : in std_logic_vector(adrw-1 downto 0):=(others=>'0');
      we : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      Dataout1 : out std_logic_vector(dw-1 downto 0):=(others=>'0');
      Dataout2 : out std_logic_vector(dw-1 downto 0):=(others=>'0'));
end regfile1;

architecture behavioral of regfile1 is
type regArray is array(0 to size-1) of std_logic_vector(dw-1 downto 0);
signal regfile : regArray;
signal RegWriteDelayed : std_logic;
signal x: std_logic_vector(31 downto 0):=(others=>'X');

begin
process(clk, reset)
begin
  if (reset = '1') then 
       for I in 0 to (size-1) loop
           for J in 0 to (dw-1) loop
                regfile(I)(J) <= '1';
           end loop;
       end loop;
  elsif (clk'event and clk='0') then
      Dataout1 <= regfile(to_integer(unsigned(rAddr1)));
      Dataout2 <= regfile(to_integer(unsigned(rAddr2)));
      RegWriteDelayed <= transport we after 1 ns;
      if (RegWriteDelayed = '1') then
         if (Datain /= x) then 
            regfile(to_integer(unsigned(wAddr))) <= Datain;
         elsif (rAddr1 = wAddr) then
             Dataout1 <= Datain;
         elsif (rAddr2 = wAddr) then
             Dataout2 <= Datain;
         end if;
      end if;
  end if;  
end process;
end behavioral;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY Control IS PORT (
   OP_5to0: IN STD_LOGIC_VECTOR(5 DOWNTO 0):=(others=>'0');
   RegDst, RegWrite, ALUSrc, Branch: out STD_LOGIC:='0';
   MemRead, MemWrite, MemtoReg: out STD_LOGIC:='0';
   ALU_op: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(others=>'0'));
END Control;

ARCHITECTURE Control_Unit of Control is
BEGIN
   with OP_5to0 select
       RegWrite <= '1' when "100011", --lw
                   '1' when "000000", --R Functions
                   '1' when "001000", --addi
                   '0' when others;
  with OP_5to0 select
        ALUSrc  <= '1' when "100011", --lw
                   '1' when "101011", --sw
                   '1' when "001000", --addi
                   '0' when others;
  with OP_5to0 select
        ALU_op  <=  "10" when "000000", --R functions
                    "01" when "000100", --beq
                    "11" when "000101", --bne
                    "00" when others;
 with OP_5to0 select
        MemWrite  <= '1' when "101011", --sw
                     '0' when others;

 with OP_5to0 select
        MemRead  <= '1' when "100011", --lw
                    '0' when others;

 with OP_5to0 select
        MemtoReg  <= '1' when "100011", --lw
                     '0' when "000000", --R instructions
                     'X' when others;

 with OP_5to0 select
        RegDst  <=  '0' when "100011", --lw
                    '0' when "001000", --addi
                    '1' when "000000", --R instructions
                    'X' when others;

 with OP_5to0 select
        Branch  <=  '1' when "000100", --beq
                    '1' when "000101", --bneq
                    '0' when others;
END Control_Unit;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY ALU_Control IS PORT (
 OP_5to0: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
 ALU_op: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
 Operation: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ALU_Control;

ARCHITECTURE AlUControl of ALU_Control is
BEGIN
    Operation(3) <= '0'; 
    Operation(2) <= ALU_op(0) or (ALU_op(1) and OP_5to0(1)); 
    Operation(1) <= not ALU_op(1) or not OP_5to0(2); 
    Operation(0) <= (OP_5to0(3) or OP_5to0(0)) and ALU_op(1);
END AlUControl;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity ALU32_exam_1 is port (
    ALUin1: in std_logic_vector(31 downto 0):=(others=>'0');
    ALUin2: in std_logic_vector(31 downto 0):=(others=>'0');
    ALUctrl: in std_logic_vector(3 downto 0):=(others=>'0');
    ALUout1: out std_logic_vector(31 downto 0):=(others=>'0');
    zero: out std_logic);
end ALU32_exam_1;

ARCHITECTURE AlU of ALU32_exam_1 is
   component FullAdder1 port (In1, In2: in std_logic_vector(31 downto 0);
                              CarryIn: in std_logic_vector(0 downto 0);
                              Sum: out std_logic_vector(31 downto 0);
                              CarryOut: out std_logic);
   end component;

   component shiftleft2 port ( In1: in std_logic_vector(31 downto 0);
                               d: out std_logic_vector(31 downto 0));
   end component;
   component FullSubtractor1 port(In1, In2: in std_logic_vector(31 downto 0);
                               Overflow: out std_logic;
                               Diff: out std_logic_vector(31 downto 0));
   end component;
   signal carryout1, Overflow1: std_logic;
   signal out_fa, slt_result, out_sh, AluOut2, out_sub: std_logic_vector(31 downto 0);

BEGIN
    FA_ALU: FullAdder1 port map(In1 => ALUin1, In2 => ALUin2, CarryIn => "0", Sum => out_fa, CarryOut => carryout1);
    SUB_ALU: FullSubtractor1 port map(In1 => ALUin1, In2 => ALUin2, Overflow => Overflow1, Diff => out_sub);
    SH_ALU: shiftleft2 port map(In1 => ALUin1, d => out_sh);
    slt_result <= x"00000001" when (to_integer(signed(ALUin1)) < to_integer(signed(ALUin2))) else
                  x"00000000";
    with ALUctrl select
      AluOut2 <= out_fa when "0010", --add
                 ALUin1 AND ALUin2 when "0000", --and
                 ALUin1 OR  ALUin2 when "0001", --or
                 out_sub when "0110", --subtract
                 slt_result when "0111", --slt
                 out_sh when "1100", --shift left
                 x"00000000" when others;

    ALUout1 <= AluOut2;
    zero <= '1' when  AluOut2 = "000" else '0';
END AlU;
[/code]
[code]
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

entity dataMemory is port (
   Addr : in std_logic_vector(31 downto 0);
   writeD : in std_logic_vector(31 downto 0);
   clk : IN std_logic;
   we : in std_logic;
   re : in std_logic;
   readD : out std_logic_vector(31 downto 0));
end dataMemory;

architecture behavioral of datamemory is
type memArray is array(0 to 63) of std_logic_vector(31 downto 0);
signal memfile : memArray;

begin
   process(clk)
    begin
     if (clk'event and clk='0') then
        if we='1' then
          memfile(to_integer(unsigned(Addr))) <= writeD;
        end if;
        if re='1' then
          readD <= memfile(to_integer(unsigned(Addr)));
        end if;
     end if;
   end process;
end behavioral;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

entity mux2to1gen is
generic (dw : natural := 32);
 port (A : in std_logic_vector(dw-1 downto 0);
       B : in std_logic_vector(dw-1 downto 0);
       s : in std_logic;
       C : out std_logic_vector(dw-1 downto 0));
end mux2to1gen; 

ARCHITECTURE multiple_mux_2to1 OF mux2to1gen IS
BEGIN
  c <= A WHEN s='1' ELSE B;
END multiple_mux_2to1;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

entity mux2_5 is
 port (A : in std_logic_vector(4 downto 0);
       B : in std_logic_vector(4 downto 0);
       s : in std_logic;
       C : out std_logic_vector(4 downto 0));
end mux2_5; 

ARCHITECTURE mux2_5 OF mux2_5 IS
 constant DataWidth : integer := 5;
 component mux2to1gen generic (dw : natural := 32);
                      port (A : in std_logic_vector(DataWidth-1 downto 0);
                            B : in std_logic_vector(DataWidth-1 downto 0);
                            s : in std_logic;
                            C : out std_logic_vector(DataWidth-1 downto 0));
 end component;

 BEGIN
  mux2_5_port_map: mux2to1gen generic map (dw => DataWidth) port map(A => A, B => B, s => s, C => C);      
END mux2_5;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

entity mux2_32 is
 port (A : in std_logic_vector(31 downto 0);
       B : in std_logic_vector(31 downto 0);
       s : in std_logic;
       C : out std_logic_vector(31 downto 0));
end mux2_32; 

ARCHITECTURE mux2_32 OF mux2_32 IS
 constant DataWidth : integer := 32;
 component mux2to1gen generic (dw : natural := 32);
                      port (A : in std_logic_vector(DataWidth-1 downto 0);
                            B : in std_logic_vector(DataWidth-1 downto 0);
                            s : in std_logic;
                            C : out std_logic_vector(DataWidth-1 downto 0));
 end component;

 BEGIN
  mux2_5_port_map: mux2to1gen generic map (dw => DataWidth) port map(A => A, B => B, s => s, C => C);      
END mux2_32;
[/code]
[code]
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY SIGN_Extension is port (
 Instr_15to0 : in std_logic_vector (15 downto 0):=(others=>'0');
 Sign_extended: out std_logic_vector (31 downto 0):=(others=>'0'));
END SIGN_Extension;

ARCHITECTURE Sign_Extender of SIGN_Extension is
  signal ones: std_logic_vector(15 downto 0):=(others=>'1');
  signal zeros: std_logic_vector(15 downto 0):=(others=>'0');
BEGIN
  Sign_extended <= ones & Instr_15to0 when Instr_15to0(15) = '1' else
                   zeros & Instr_15to0 when Instr_15to0(15) = '0';
END Sign_Extender;
[/code]

And this for MIPS:

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;

entity mips is port (clk: in std_logic;
                     reset: in std_logic;
                     outmips: out std_logic_vector(31 downto 0));
end mips;

architecture mips_architecture of mips is
  constant dw1: integer := 32;
  constant adrw1: integer := 5;
  constant size1 :integer := 20;
  component ALU32_exam_1 port(ALUin1: in std_logic_vector(31 downto 0);
                              ALUin2: in std_logic_vector(31 downto 0);
                              ALUctrl: in std_logic_vector(3 downto 0);
                              ALUout1: out std_logic_vector(31 downto 0);
                              zero: out std_logic);
  end component;

  component regfile1 generic (dw : natural := 4; size : natural := 20; adrw : natural := 2);
                     port (Datain : in std_logic_vector(dw1-1 downto 0);
                           rAddr1 : in std_logic_vector(adrw1-1 downto 0);
                           rAddr2 : in std_logic_vector(adrw1-1 downto 0);
                           wAddr : in std_logic_vector(adrw1-1 downto 0);
                           we : in std_logic;
                           clk : in std_logic;
                           reset : in std_logic;
                           Dataout1 : out std_logic_vector(31 downto 0);
                           Dataout2 : out std_logic_vector(31 downto 0));
  end component;
  
  component instrMemory port(Addr : in std_logic_vector(31 downto 0);
                             C : out std_logic_vector(31 downto 0));
  end component;

  component Control port( OP_5to0: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
                          RegDst, RegWrite, ALUSrc, Branch: out STD_LOGIC;
                          MemRead, MemWrite, MemtoReg: out STD_LOGIC;
                          ALU_op: OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
  end component;

  component ALU_Control port(OP_5to0: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
                             ALU_op: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                             Operation: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  end component;

  component pc port(inPC: in std_logic_vector(31 downto 0);
                    outPC: out std_logic_vector(31 downto 0);
                    clk: in std_logic;
                    reset: in std_logic);
  end component;

  component FullAdder1 port (In1, In2: in std_logic_vector(31 downto 0);
                          CarryIn: in std_logic_vector(0 downto 0);
                          Sum: out std_logic_vector(31 downto 0);
                          CarryOut: out std_logic);
  end component;
  
  component dataMemory port(Addr : in std_logic_vector(31 downto 0);
                             writeD : in std_logic_vector(31 downto 0);
                             clk : IN std_logic;
                             we : in std_logic;
                             re : in std_logic;
                             readD : out std_logic_vector(31 downto 0));
  end component;

  component MUX2_5 port (A : in std_logic_vector(4 downto 0);
                         B : in std_logic_vector(4 downto 0);
                         s : in std_logic;
                         C : out std_logic_vector(4 downto 0));
  end component;

  component MUX2_32 port (A : in std_logic_vector(31 downto 0);
                         B : in std_logic_vector(31 downto 0);
                         s : in std_logic;
                         C : out std_logic_vector(31 downto 0));
  end component;


  component SIGN_Extension port (Instr_15to0 : in std_logic_vector (15 downto 0);
                               Sign_extended: out std_logic_vector (31 downto 0));
  end component;
     
  signal PC_FA: std_logic_vector(31 downto 0);
  signal FA_PC_OUT: std_logic_vector(31 downto 0);
  signal OUT_IM: std_logic_vector(31 downto 0);
  signal Datain: std_logic_vector(31 downto 0);
  signal DataOut1_1: std_logic_vector(31 downto 0);
  signal DataOut2_1: std_logic_vector(31 downto 0);
  signal we, zero: std_logic := '0';
  signal RegDst, ALUSrc, Branch, BranchTaken, Jump: STD_LOGIC;
  signal MemRead, MemWrite, MemtoReg: STD_LOGIC;
  signal ALU_op: STD_LOGIC_VECTOR(1 DOWNTO 0);
  signal ALUControl_out: STD_LOGIC_VECTOR(3 DOWNTO 0);
  signal MUX_ALU_OUT: STD_LOGIC_VECTOR(31 DOWNTO 0); 
  signal outALU: STD_LOGIC_VECTOR(31 DOWNTO 0);
  signal outRam: STD_LOGIC_VECTOR(31 DOWNTO 0);
  signal Four: STD_LOGIC_VECTOR(31 DOWNTO 0);
  signal SignExOutAligned,SignExOut,ALUBranchOut : std_logic_vector(31 downto 0);
  signal ShiftJump2MuxJump, MuxBranch2MuxJump, MuxJump2C: std_logic_vector(31 downto 0);
  signal Mux_Reg_Out: std_logic_vector(4 downto 0);

 BEGIN
  Four <= std_logic_vector(to_unsigned(4,32));
  SignExOutAligned <= SignExOut(29 downto 0) & "00";
  FA_PC: FullAdder1 port map(In1 => PC_FA, In2 => Four, CarryIn => "0", Sum => FA_PC_OUT);
  FA_Branch: FullAdder1 port map(In1 => FA_PC_OUT, In2 => SignExOutAligned, CarryIn => "0", Sum => ALUBranchOut);
  program_counter: pc port map(inPC => MuxBranch2MuxJump, outPC => PC_FA, clk => clk, reset => reset);
  InstructionMemory: instrMemory port map(Addr => PC_FA, C => OUT_IM);
  RegisterFile: regfile1 generic map (dw =>dw1, size =>size1, adrw =>adrw1)  port map(Datain => Datain,  
                                  rAddr1 => OUT_IM(25 downto 21),
                                  rAddr2 => OUT_IM(20 downto 16),
                                  wAddr => Mux_Reg_Out,
                                  we => we,
                                  clk => clk,
                                  reset => reset,
                                  Dataout1 => DataOut1_1,
                                  Dataout2 => Dataout2_1);
   ControlUnit: Control port map(OP_5to0 => OUT_IM(31 downto 26),
                                 RegDst => RegDst, 
                                 RegWrite => we, 
                                 ALUsrc=> ALUSrc, 
                                 Branch => Branch,
                                 MemRead => MemRead, 
                                 MemWrite => MemWrite, 
                                 MemtoReg => MemToReg,
                                 ALU_op => ALU_op);
   ALUControl: ALU_Control port map(OP_5to0 => OUT_IM(5 downto 0),
                                    ALU_op => ALU_op,
                                    Operation => ALUControl_out);
   ALU32: ALU32_exam_1 port map(ALUin1 => DataOut1_1,
                                ALUin2 => MUX_ALU_OUT,
                                ALUctrl => ALUControl_out,
                                ALUout1 => outALU,
                                zero => zero); 
   RAM: dataMemory port map(Addr => outALU,
                            writeD => Dataout2_1,
                            clk => clk,
                            we => MemWrite,
                            re => MemRead,
                            readD => outRam);
   MUXReg: MUX2_5 port map(A => OUT_IM(20 downto 16),
                           B => OUT_IM(15 downto 11),
                           s => RegDst,
                           C => Mux_Reg_Out);
   MUXALUIN: MUX2_32 port map(A =>Dataout2_1,
                              B => SignExOut,
                              s => ALUSrc,
                              C => MUX_ALU_OUT);
   MUXRAM: MUX2_32 port map(A =>outALU,
                            B => outRam,
                            s => MemToReg,
                            C => Datain);
   ShiftJump2MuxJump <= FA_PC_OUT(31 downto 28) & OUT_IM(25 downto 0) & "00";
   BranchTaken <= Branch and Zero;
   MuxBranch: MUX2_32 port map(A => FA_PC_OUT,
                             B => ALUBranchOut,
                             s => BranchTaken,
                             C => MuxBranch2MuxJump);
   SignEx: SIGN_Extension port map(Instr_15to0 => OUT_IM(15 downto 0),
                                  Sign_extended => SignExOut);
  outmips <= outALU;
end mips_architecture;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_mips IS
END tb_mips;
 
ARCHITECTURE tb_mips OF tb_mips IS 
  
   COMPONENT mips PORT(clk: in std_logic;
                        reset: in std_logic;
                        outmips: out std_logic_vector(31 downto 0));
   END COMPONENT;
    
   signal clk1, reset1 : std_logic;
   signal outmips1: std_logic_vector(31 downto 0);
 
BEGIN
   mips_port: mips PORT MAP (clk => clk1, reset => reset1, outmips => outmips1);

   stim_proc: process
           variable clktmp: std_logic := '1';
           variable resetmp: std_logic := '1';
     begin
       clktmp := NOT clktmp;
       clk1 <= clktmp;
       if (resetmp = '1') then
         reset1 <= resetmp;
         resetmp := '0';
       else
         reset1 <= '0';
       end if;
       wait for 50 ns;      
   end process;
END;